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Basic knowledge of integrated circuit packaging ——-SOP packaging (IV)
Release time:2017-03-04
Basic knowledge of integrated circuit packaging ---SOP packaging (iv)
Last time we talked about DIP packaging in the 1970s, but by the early 1980s, SMT(Surface Mount Technology) had become popular, and the packaging pins began to change, gradually deriving the SOP packaging form from the DIP straight insertion.
What is SOP encapsulation?
SOP: Small Outline Package (Small shape Package) a surface-mounted Package in which the pin is drawn from two longer sides of the chip and the end of the pin extends outward like a gull wing. The diagram below:
Naming rules for SOP
The encapsulation of SOP is named as DIP, and the number of pins in the rear represents the number of pins in the package, such as SOP8, 8 represents the number of pins (4 pins on each side).
Common types of SOP
SOP's "alternative" encapsulation
1. SOJ packaging
The full name of SOJ: Small Outline j-lead (Small size j-shaped pin package). The pin is drawn from both sides of the package and is downward in the shape of J. Mainly used in memory, as shown below
2. SOIC packaging
Small Outline Integrated Circuit (Small external chip) is an Integrated Circuit (SOIC=SOP). However, according to the data of various factories, it is found that its size is divided into wide and narrow. Take SN74HC595 of TI as an example, as shown in the figure below:
It is shown in its PDF file that SOIC16 comes in two sizes: wide and narrow. After burning the small universe of science and engineering, we finally found that the standards SOIC follows (JEDEC and EIAJ standards) are different, resulting in the same packaging but different sizes.
JEDEC and EIAJ standards
The full name of JEDEC is the Joint Electronic Devices Engineering Council, which was established in 1958. EIAJ's full name is Electronic Industries Association Japan, founded in 1948. The two set standards for the electronics industry, but the EIAJ standard's SOIC body width is 5.3mm, while the JEDEC standard's SOIC body width is 3.8mm or 7.5mm, which also leads to the size difference of the SOIC. This difference is mainly reflected in the width WB and WL, as shown in the following table:
Last time we talked about DIP packaging in the 1970s, but by the early 1980s, SMT(Surface Mount Technology) had become popular, and the packaging pins began to change, gradually deriving the SOP packaging form from the DIP straight insertion.
What is SOP encapsulation?
SOP: Small Outline Package (Small shape Package) a surface-mounted Package in which the pin is drawn from two longer sides of the chip and the end of the pin extends outward like a gull wing. The diagram below:
Naming rules for SOP
The encapsulation of SOP is named as DIP, and the number of pins in the rear represents the number of pins in the package, such as SOP8, 8 represents the number of pins (4 pins on each side).
Common types of SOP
SOP's "alternative" encapsulation
1. SOJ packaging
The full name of SOJ: Small Outline j-lead (Small size j-shaped pin package). The pin is drawn from both sides of the package and is downward in the shape of J. Mainly used in memory, as shown below
2. SOIC packaging
Small Outline Integrated Circuit (Small external chip) is an Integrated Circuit (SOIC=SOP). However, according to the data of various factories, it is found that its size is divided into wide and narrow. Take SN74HC595 of TI as an example, as shown in the figure below:
It is shown in its PDF file that SOIC16 comes in two sizes: wide and narrow. After burning the small universe of science and engineering, we finally found that the standards SOIC follows (JEDEC and EIAJ standards) are different, resulting in the same packaging but different sizes.
JEDEC and EIAJ standards
The full name of JEDEC is the Joint Electronic Devices Engineering Council, which was established in 1958. EIAJ's full name is Electronic Industries Association Japan, founded in 1948. The two set standards for the electronics industry, but the EIAJ standard's SOIC body width is 5.3mm, while the JEDEC standard's SOIC body width is 3.8mm or 7.5mm, which also leads to the size difference of the SOIC. This difference is mainly reflected in the width WB and WL, as shown in the following table:
